1. Field of the Invention
The present invention is generally directed to the field of semiconductor devices, and, more particularly, to a contact resistance test structure and methods of using same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such tran-sistors.
FIG. 1A is a cross-sectional view of an illustrative transistor 10 formed above a semiconducting substrate 12. The transistor 10 is generally comprised of a gate electrode 14, a gate insulation layer 16, source/drain regions 20 and a sidewall spacer 22. An illustrative trench isolation structure 18 is formed in the substrate 12 to electrically isolate the transistor 10 from adjacent semiconductor devices, e.g., other transistors. Conductive contacts 26 are formed in a layer of insulating material 24. The contacts 26 are the means by which a conductive electrical path is established with the source/drain regions 20. The illustrative transistor 10 depicted in FIG. 1A may be formed in accordance with various techniques that are well known to those skilled in the art.
It should be understood that the transistor 10 in FIG. 1A is depicted in an ideal state that may or may not correspond to devices that have actually been manufactured using a variety of complex process flows. More specifically, in FIG. 1A, the entirety of the contact area 25 of the contact 26 engages the source/drain region 20. However, as device dimensions have continued to shrink, it is becoming increasingly difficult to insure that the entirety of the contact area 25 contacts the desired region, i.e., the source/drain region 20. Additionally, due to device size reductions and increased density, it is becoming more difficult to precisely align one structure, e.g., the contact 26, with the desired contact region, e.g., the source/drain region 20, without interfering with other structures.
For example, FIG. 1B depicts an illustrative example wherein the contacts 26 are at least partially formed on the sidewall spacer 22 of the transistor 10. In this illustrative situation, the contact area 25A is less than the idealized or theoretical contact area 25 shown in FIG. 1A. Accordingly, the contact resistance will increase in proportion to the size of the contact area 25 relative to the contact area 25A. FIG. 1C depicts another illustrative example in which a plurality of gate electrode structures share a common active region, e.g., a doped source/drain region 20. Similar to the situation depicted in FIG. 1B, the contact area 25A of the contacts 26 in FIG. 1C is less than the idealized or theoretical contact area 25 shown in FIG. 1A. In the particular example depicted in FIG. 1C, the close positioning of the gate electrode structures 14 and the size of the spacer 22 leave very little room, e.g., 10-100 nm, between the spacer 22 on adjacent devices. Such densely packed structures make it difficult to manufacture devices in which the entire area 25 fully engages the desired contact regions, i.e., a source/drain region. Such variations in contact resistance in actual devices as compared to contact resistance determined from an assumption that the contacts 26 fully contact the desired area (as shown in FIG. 1A) may lead to device performance that is less than anticipated or desired.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.